Various receiver architectures for a full-duplex multi-level PAM (Pulse Amplitude Modulation) with applications in Gigabit Ethernet transceiver implementation have been proposed in, for example, an U.S. patent entitled “Multi-Pair Gigabit Ethernet Transceiver” by Agazzi et al. (U.S. Pat. No. 6,771,752), an U.S. patent entitled “Symbol Encoding and Decoding Architecture for Trellis-Coded Modulation in Gigabit Ethernet” by Bhoja (U.S. Pat. No. 6,731,692) and a publication entitled “The IntelliRate Architecture” by Agere Systems in 2003. All of these architectures employ a sample rate that equals exactly the baud-rate (fb) or twice the baud-rate (2fb). The use of baud rate sampling requires that the receiving signal be sampled at the optimum timing phase location at the Analog-to-Digital Converter (ADC) output, and thus requires complex phase selection circuit in the analog domain. As pointed out in the above paper titled “The IntelliRate Architecture”, the analog phase selection circuit can be removed by doubling the speed of the ADC and by using a digital equalizer to compensate for both the timing phase misalignment and channel distortion. Although removing the phase selection circuit reduces the analog circuit complexity, the use of a double speed ADC inevitably increases the ADC complexity. For example, the baud rate of Gigabit Ethernet is 125 MHz and the realization of a 250 MHz ADC with high bit resolution is very demanding. Thus, there is a need for receiver architecture with flexible sampling rate that eliminates the use of a complex analog phase selection circuit without doubling the speed of the ADC.
Moreover, for a full-duplex PAM system, a portion of the transmitting signal echoes back from the hybrid circuit to the receiver front-end. This echo must be cancelled before the receiving signal can be demodulated, such problem is addressed for example in a paper called ““An Echo Cancellation Based 4800 Bit/s Full-Duplex DDD Modem” by Werner, J.-J. in IEEE Journal on Selected Areas in Communications in 1984. For the conventional baud rate receiver structure, such as the one disclosed in the above paper, a baud-rate digital echo canceller is used to cancel the echo after the ADC. This can be replaced by a fractional baud rate digital echo canceller for the underlining receiver architecture. The fractional baud-rate echo canceller has the capability of removing out-of-band noise coupled with the echo and thus offers better noise rejection performance over the baud-rate echo canceller
After the echo is cancelled, the receiving signal must be sampled at the correct timing phase before channel equalization can be performed in order to obtain optimum signal-to-noise performance at the equalizer output. At the start-up stage of the receiver, the receiver is totally “blind” in that it does not sample the signal at the correct timing neither does it have the correct equalizer coefficients to equalize the channel distortion. Conventional approach uses a decision feedback equalizer (DFE) with a soft level slicer to effectively achieve a “blind” start-up, but such construction possesses the error propagation problem as a result of decision error when the receiver operates under more severe noise environment. Prior work has been proposed to reduce this error effect by combing the DFE with a Viterbi decoder, such as in a paper by Erich F. Haratsch, titled ““A 1-Gb/s Joint Equalizer and Trellis Decoder for 1000BASE-T Gigabit Ethernet” of IEEE Journal of Solid-State Circuits in 2001 and in the two previously mentioned U.S. patents (U.S. Pat. Nos. 6,771,752 and 6,731,692). However, this implementation of combining the DFE with a Viterbi decoder is nonetheless complex. Thus, there is a further need for a fast “blind” start-up equalization in a receiver while at the same time addressing the error propagation problem associated with the traditional DFE.